Many diverse test data compression techniques are widely recognized as essential to reduce the overall test cost. In these schemes, a tester delivers compressed test patterns by using a small number of input channels while an on-chip decompressor expands them into data loaded into scan chains. The actual encoding methods typically take advantage of low test pattern fill rates. In principle, two fundamental test compression paradigms coexist. Single-phase methods, such as broadcast scan, Illinois scan, VirtualScan, or adaptive scan, employ very simple decompressors, often comprising just hardwired or reconfigurable fan-outs. These fan-outs constrain ATPG (automatic test pattern generation) by defining either temporary or permanent equivalence of scan cells. As soon as one of the scan cells gets a value assigned by ATPG, the value is automatically copied to all other equivalent scan cells. Consequently, there is no need for a separate encoding phase.
The second class includes two-phase methods represented by combinational compression, and LFSR (Linear Feedback Shift Register) coding, which subsequently evolved first into static LFSR reseeding, and then into dynamic LFSR reseeding. In particular, the Embedded Deterministic Test (EDT)—a peculiar form of dynamic reseeding—has gained broad acceptance as a reliable industrial solution. Here, ATPG first generates partially specified test cubes with many don't-care positions (unspecified bits). Subsequently these test cubes are encoded using a variety of techniques. For example, reseeding and EDT use a solver of linear equations. Until now test generation within this class was done without ATPG taking into account any information about the decompressor or the implications it might introduce. An early strategy to change this trend was to exclusively modify ATPG so that justification of certain decision nodes is delayed and combined with LFSR seed computation.
In addition to reducing data volume, test time, and test pin counts, the test compression schemes have been used successfully to limit test power dissipation. Scan toggling can consume more power than a circuit is rated for. Balancing test performance against the power consumption in a given design is therefore a challenge. Since don't-care bits are typically filled with random values, the amount of toggling during test may result in a power droop that would not occur in the chip's mission mode. The bulk of test power consumption is also attributed to unloading test responses. Consequently, the power dissipation can increase by a factor of 2-3 compared to the functional mode, and is only expected to worsen with scan patterns already consuming 30× over the mission mode's peak power. The resulting higher junction temperature and increased peak power can lead to overheating or supply voltage noise—either of which can cause a device malfunction, loss of yield, chip reliability degradation, shorter product lifetime, or a device permanent damage. Over the years, numerous techniques for power reduction during scan testing have been proposed. A thorough survey of these methods can be found in a book, “Power-Aware Testing and Test Strategies for Low Power Devices”, P. Girard, N. Nicolici, and X. Wen (ed.), Springer, N.Y. 2010.
On-chip test compression is facing similar problems as far as test power is concerned. An encoding scheme should therefore allow feeding scan chains with patterns having reduced the amount of toggling. In response to these challenges, several low power test data encoding schemes were developed. Some of them rest on conventional LFSR reseeding techniques with certain extensions reducing the scan-in transition probability. In particular, the method disclosed in, “Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding,” P. M. Rosinger, B. M. Al-Hashimi, and N. Nicolici, Proc. ICCD, pp. 474-479, 2002, uses two LFSRs whose outputs are AND-ed or OR-ed to produce actual test cubes and to decrease the amount of switching. The scheme disclosed in “Low power test data compression based on LFSR reseeding,” J. Lee and N. A. Touba, Proc. ICCD, pp. 180-185, 2004, divides test cubes into blocks and only uses reseeding to encode blocks that contain transitions so that extra seeds do not compromise compression ratios. Another method, disclosed in “Low power test data application in EDT environment through decompressor freeze”, D. Czysz, G. Mrugalski, J. Rajski, and J. Tyszer, IEEE Trans. CAD, vol. 27, pp. 1278-1290, July 2008, reduces the test power by using available encoding capacity to limit transitions in scan chains. Unlike reseeding, this technique freezes a decompressor in certain states, which allows loading scan chains with patterns having low transition counts. A low power decompressor disclosed in “New test data decompressor for low power applications,” G. Mrugalski, J. Rajski, D. Czysz, and J. Tyszer, Proc. DAC, pp. 539-544, 2007, used in parallel with a power-aware scan controller (“Low power scan operation in test data compression environment”, D. Czysz, M. Kassab, X. Lin, G. Mrugalski, J. Rajski, and J. Tyszer, IEEE Trans. CAD, vol. 28, pp. 1742-1755, November 2009), allows further reduction of toggling rates when feeding scan chains with decompressed test patterns.
Several solutions deployed or adapted in the low power test compression have originally debuted as stand-alone methods trying to tailor patterns to the requirements of tests with a reduced switching activity. These power-aware schemes assign certain non-random values to unspecified positions of test cubes causing power violations. Such don't-care bits, due to low fill rates, may also assume values minimizing the amount of transitions during scan-in shifting. The resultant runs of constant values can be encoded using run-length codes. Alternatively, a minimum transition fill replicates the value of the most recent care bit for all unspecified positions until the next care bit (specified bit). A vector modification (S. Kajihara, K. Ishida, and K. Miyase, “Test vector modification for power reduction during scan testing,” Proc. VTS, pp. 160-165, 2002) and California scan architecture (K. Y. Cho, S. Mitra, and E. J. McCluskey, “California scan architecture for high quality and low power testing,” Proc. ITC, paper 25.3, 2007) proceed along similar lines. The minimum transition fill (R. Sankaralingam and N. A. Touba, “Controlling peak power during scan testing,” Proc. VTS, pp. 153-159, 2002) helps in handling unspecified positions whose locations are determined by bit stripping which checks whether turning a given bit into unspecified one will affect fault coverage. Other forms of filling capture power by assigning particular values to unspecified bits so that the number of transitions at the outputs of scan cells in the capture mode is minimized.
Challenges remain in both reducing data volume, test time, and test pin counts and lowing test power dissipation, it is desirable to develop a testing technology that can elevate compression ratios and reduce switching rates in scan chains.